Semiconductor light emitting device, nitride semiconductor layer growth substrate, and nitride semiconductor wafer

ABSTRACT

According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type and having a major surface, a second semiconductor layer of a second conductivity type, and a light emitting layer provided between the first and second semiconductor layers. The major surface is opposite to the light emitting layer. The first semiconductor layer has structural bodies provided in the major surface. The structural bodies are recess or protrusion. A centroid of a first structural body aligns with a centroid of a second structural body nearest the first structural. hb, rb, and Rb satisfy rb/(2·hb)≦0.7, and rb/Rb&lt;1, where hb is a depth of the recess, rb is a width of a bottom portion of the recess, and Rb is a width of the protrusion.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a division of and claims the benefit of priorityunder 35 U.S.C. §120 from U.S. Ser. No. 14/330,151 filed Jul. 14, 2014,which is a division of U.S. Ser. No. 13/404,553 filed Feb. 24, 2012 (nowU.S. Pat. No. 8,823,016 issued Sep. 2, 2014), and claims the benefit ofpriority under 35 U.S.C. §119 from Japanese Patent Application No.2011-115583 filed May 24, 2011; the entire contents of each of which areincorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor lightemitting device, a nitride semiconductor layer growth substrate, and anitride semiconductor wafer.

BACKGROUND

Semiconductor light emitting devices such as ultraviolet, blue, or greenlight emitting diodes (LEDs) and bluish-violet or blue laser diodes(LDs) that use nitride semiconductors such as gallium nitride and thelike have been developed.

It is desirable to increase the external quantum efficiency to increasethe luminous efficiency of nitride semiconductor light emitting devices.To increase the external quantum efficiency, it is important to increasethe light extraction efficiency.

There exists a configuration to increase the light extraction efficiencyby patterning an unevenness in a substrate used to grow the nitridesemiconductor layer. In such a configuration, there are cases where pitsform when filling the unevenness, the surface flatness degrades, and theexternal quantum efficiency decreases.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross-sectional view illustrating a semiconductorlight emitting device according to a first embodiment;

FIG. 2A and FIG. 2B are schematic plan views illustrating thesemiconductor light emitting device according to the first embodiment;

FIG. 3 is a schematic cross-sectional view illustrating thesemiconductor light emitting device according to the first embodiment;

FIG. 4 is a schematic cross-sectional view illustrating a portion of thesemiconductor light emitting device according to the first embodiment;

FIG. 5A to FIG. 5F are electron microscope images and schematic viewsillustrating states of crystal layers of a first sample and a secondsample;

FIG. 6 is an electron microscope photograph illustrating the state ofthe crystal layer of the first sample;

FIG. 7A to FIG. 7D are schematic cross-sectional views illustratingstates of the crystal layers of the first sample and the second sample;

FIG. 8 is a cross section scanning electron microscope photographillustrating the state of the crystal layer of the first sample;

FIG. 9 is a table illustrating the configurations of the substrates usedin the experiment and the characteristics of the crystal layers grown onthe substrates;

FIG. 10, FIG. 11A, and FIG. 11B are graphs illustrating thecharacteristics of the semiconductor light emitting devices of theexample and the reference example;

FIG. 12 is a schematic cross-sectional view illustrating theconfiguration of another semiconductor light emitting device accordingto the first embodiment;

FIG. 13A and FIG. 13B are schematic plan views illustrating anothersemiconductor light emitting device according to the first embodiment;

FIG. 14A to FIG. 14H and FIG. 15A to FIG. 15H are schematic plan viewsillustrating semiconductor light emitting devices according to the firstembodiment; and

FIG. 16A and FIG. 16B are schematic cross-sectional views illustrating anitride semiconductor wafers according to a third embodiment.

DETAILED DESCRIPTION

According to one embodiment, a semiconductor light emitting deviceincludes a first semiconductor layer including a layer of a firstconductivity type and having a first major surface; a secondsemiconductor layer including a layer of a second conductivity typedifferent from the first conductivity type; and a light emitting layerprovided between the first semiconductor layer and the secondsemiconductor layer. The first major surface is on a side of the firstsemiconductor layer opposite to the light emitting layer. The firstsemiconductor layer has a plurality of structural bodies provided in thefirst major surface. Each of the structural bodies is a recess providedon the first major surface with a protrusion provided between thestructural bodies, or each of the structural bodies is a protrusionprovided on the first major surface with a recess provided between thestructural bodies. The structural bodies include a first structural bodyand a second structural body nearest the first structural body whenviewed along a first axis perpendicular to the first major surface. Aconfiguration of the first structural body when viewed along the firstaxis has a first centroid. A configuration of the second structural bodywhen viewed along the first axis has a second centroid. The firstcentroid aligns with the second centroid along a second axisperpendicular to the first axis. hb, rb, and Rb satisfy rb/(2·hb)≦0.7,and rb/Rb<1, where hb is a depth of the recess, rb is a width of abottom portion of the recess along the second axis, and Rb is a width ofthe protrusion along the second axis.

According to another embodiment, a nitride semiconductor layer growthsubstrate has a substrate major surface and a plurality of substratestructural bodies provided in the substrate major surface. The substratemajor surface is used to grow a nitride semiconductor layer. Each of thesubstrate structural bodies is a substrate protrusion provided on thesubstrate major surface with a substrate recess provided between thesubstrate structural bodies, or each of the substrate structural bodiesis a substrate recess provided on the substrate major surface with asubstrate protrusion provided between the substrate structural bodies.The substrate structural bodies include a first substrate structuralbody and a second substrate structural body nearest the first substratestructural body when viewed along a first axis perpendicular to thesubstrate major surface. A configuration of the first substratestructural body when viewed along the first axis has a first centroid. Aconfiguration of the second substrate structural body when viewed alongthe first axis has a second centroid. The first centroid aligns with thesecond centroid along a second axis perpendicular to the first axis. ha,ra, and Ra satisfy ra/(2·ha)≦0.7, and ra/Ra<1, where ha is a height ofthe substrate protrusion, ra is a width of a substrate apical portion ofthe substrate protrusion along the second axis, and Ra is a width of thesubstrate recess along the second axis.

According to another embodiment, a nitride semiconductor wafer includesa substrate and a nitride semiconductor layer. The substrate has asubstrate major surface and a plurality of substrate structural bodiesprovided in the substrate major surface. The nitride semiconductor layeris provided on the substrate major surface. The substrate structuralbodies contact the nitride semiconductor layer. Each of the substratestructural bodies is a substrate protrusion provided on the substratemajor surface with a substrate recess provided between the substratestructural bodies, or each of the substrate structural bodies is asubstrate recess provided on the substrate major surface with asubstrate protrusion provided between the substrate structural bodies.The substrate structural bodies include a first substrate structuralbody and a second substrate structural body nearest the first substratestructural body when viewed along a first axis perpendicular to thesubstrate major surface. A configuration of the first substratestructural body when viewed along the first axis has a first centroid. Aconfiguration of the second substrate structural body when viewed alongthe first axis has a second centroid. The first centroid aligns with thesecond centroid along a second axis perpendicular to the first axis. ha,ra, and Ra satisfy ra/(2·ha)≦0.7, and ra/Ra<1, where ha is a height ofthe substrate protrusion, ra is a width of a substrate apical portion ofthe substrate protrusion along the second axis, and Ra is a width of thesubstrate recess along the second axis.

Various embodiments will be described hereinafter with reference to theaccompanying drawings.

The drawings are schematic or conceptual; and the relationships betweenthe thicknesses and the widths of portions, the proportions of sizesbetween portions, and the like are not necessarily the same as theactual values thereof. Further, the dimensions and the proportions maybe illustrated differently among the drawings, even for identicalportions.

In the specification and the drawings of the application, componentssimilar to those described in regard to a drawing thereinabove aremarked with like reference numerals, and a detailed description isomitted as appropriate.

First Embodiment

FIG. 1 is a schematic cross-sectional view illustrating theconfiguration of a semiconductor light emitting device according to afirst embodiment. FIG. 2A and FIG. 2B are schematic plan viewsillustrating the configuration of the semiconductor light emittingdevice according to the first embodiment.

FIG. 3 is a schematic cross-sectional view illustrating theconfiguration of the semiconductor light emitting device according tothe first embodiment. First, an overview of the configuration of thesemiconductor light emitting device according to the embodiment will bedescribed using FIG. 3.

As illustrated in FIG. 3, the semiconductor light emitting device 110according to the embodiment includes a first semiconductor layer 10, asecond semiconductor layer 20, and a light emitting layer 30.

The first semiconductor layer 10 includes a layer of a firstconductivity type. The second semiconductor layer 20 includes a layer ofa second conductivity type. The second conductivity type differs fromthe first conductivity type. The light emitting layer 30 is providedbetween the first semiconductor layer 10 and the second semiconductorlayer 20.

For example, the first semiconductor layer 10, the second semiconductorlayer 20, and the light emitting layer 30 include a nitridesemiconductor.

For example, the first conductivity type is an n type; and the secondconductivity type is a p type. However, the embodiment is not limitedthereto. The first conductivity type may be the p type; and the secondconductivity type may be the n type. Hereinbelow, the case is describedwhere the first conductivity type is the n type and the secondconductivity type is the p type.

Herein, a direction from the first semiconductor layer 10 toward thesecond semiconductor layer 20 is taken as a Z-axis direction. The Z-axisis taken as a first axis. One axis perpendicular to the Z-axis is takenas an X-axis. A direction perpendicular to the Z-axis and the X-axis istaken as a Y-axis. For convenience of description herein, “up” may referto a direction from the first semiconductor layer 10 toward the secondsemiconductor layer 20, and “down” may refer to a direction from thesecond semiconductor layer 20 toward the first semiconductor layer 10.

The Z-axis is parallel to the stacking direction of the firstsemiconductor layer 10, the light emitting layer 30, and the secondsemiconductor layer 20 in a semiconductor structural body 10 s (anitride semiconductor layer) that includes the first semiconductor layer10, the light emitting layer 30, and the second semiconductor layer 20.

In the specification of the application, stacking includes not only thecase of being overlaid in direct contact but also the case of beingoverlaid with another component inserted therebetween.

In this example, the semiconductor structural body 10 s further includesa multilayered film body 40. The multilayered film body 40 is providedbetween the first semiconductor layer 10 and the light emitting layer30. The multilayered film body 40 is, for example, a superlattice layer.The multilayered film body 40 is, for example, the n type. Themultilayered film body 40 may be provided if necessary and may beomitted. The multilayered film body 40 can be considered to be includedin the first semiconductor layer 10.

In this example, the first semiconductor layer 10 includes a bufferlayer 55, a foundation layer 60, and an n-side contact layer 11. Thefoundation layer 60 is provided between the buffer layer 55 and thelight emitting layer 30. The n-side contact layer 11 is provided betweenthe foundation layer 60 and the light emitting layer 30. The bufferlayer 55 may include, for example, a GaN layer. The foundation layer 60may include, for example, an undoped GaN layer. The n-side contact layer11 may include, for example, an n-type GaN layer. The n-side contactlayer 11 corresponds to a layer of the first conductivity type includedin the first semiconductor layer 10.

In this example, the second semiconductor layer 20 includes a firstp-side layer 21, a second p-side layer 22, and a third p-side layer 23.The light emitting layer 30 is provided between the first p-side layer21 and the first semiconductor layer 10. The second p-side layer 22 isprovided between the first p-side layer 21 and the light emitting layer30. The third p-side layer 23 is provided between the second p-sidelayer 22 and the light emitting layer 30.

The first p-side layer 21 functions as, for example, a p-side contactlayer. The first p-side layer 21 may include, for example, a p-type GaNlayer. The second p-side layer 22 may include, for example, a p-type GaNlayer. The third p-side layer 23 may include, for example, a p-typeAlGaN layer. The first p-side layer 21, the second p-side layer 22, andthe third p-side layer 23 correspond to a layer of the secondconductivity type included in the second semiconductor layer 20.

Examples of the light emitting layer 30 and the multilayered film body40 are described below.

In this example, the semiconductor light emitting device 110 furtherincludes a substrate 50. The first semiconductor layer 10 is providedbetween the substrate 50 and the light emitting layer 30. The Z-axis isperpendicular to a major surface (a substrate major surface 50 a) of thesubstrate 50. The substrate 50 may include, for example, sapphire,silicon carbide (SiC), a silicon (Si) substrate, gallium arsenide(GaAs), and the like.

For example, the semiconductor structural body 10 s is formed on themajor surface (the substrate major surface 50 a) of the substrate 50.Namely, the buffer layer 55 is formed on the substrate major surface 50a; the foundation layer 60 is formed on the buffer layer 55; the n-sidecontact layer 11 is formed on the foundation layer 60; the lightemitting layer 30 is formed on the n-side contact layer 11; and thesecond semiconductor layer 20 is formed on the light emitting layer 30.The substrate 50 may be separated after the semiconductor structuralbody 10 s is formed on the substrate major surface 50 a of the substrate50. The buffer layer 55 may be removed when separating the substrate 50.At least a portion of the buffer layer 55 may remain after separatingthe substrate 50. The buffer layer 55 may be provided if necessary andmay be omitted in some cases.

The first semiconductor layer 10 has a first major surface 60 a on theside of the first semiconductor layer 10 opposite to the light emittinglayer 30. The first major surface 60 a is a surface facing the substrate50. The first major surface 60 a contacts the substrate major surface 50a. In this example, the first major surface 60 a is a surface (the lowersurface) of the buffer layer 55. However, as described above, forexample, the first major surface 60 a is a surface (the lower surface)of the foundation layer 60 in the case where the substrate 50 isseparated from the semiconductor structural body 10 s.

The semiconductor light emitting device 110 further includes a firstelectrode 70 and a second electrode 80. The first electrode 70 iselectrically connected to the first semiconductor layer 10(specifically, the n-side contact layer 11). The second electrode 80 iselectrically connected to the second semiconductor layer 20(specifically, the first p-side layer 21).

In this example, the light emitting layer 30 is provided between thesecond semiconductor layer 20 and a portion of the first semiconductorlayer 10. The first electrode 70 is provided on a portion of the firstsemiconductor layer 10 of the major surface of the semiconductorstructural body 10 s on the second semiconductor layer 20 side.

Light is emitted from the light emitting layer 30 by a current flowingin the light emitting layer 30 via the first semiconductor layer 10 andthe second semiconductor layer 20 by applying a voltage between thefirst electrode 70 and the second electrode 80. The semiconductor lightemitting device 110 is, for example, an LED.

An example of the configuration of the light emitting layer 30 will nowbe described.

FIG. 4 is a schematic cross-sectional view illustrating theconfiguration of a portion of the semiconductor light emitting deviceaccording to the first embodiment.

As illustrated in FIG. 4, the light emitting layer 30 includes multiplebarrier layers 31 and a well layer 32 provided between the multiplebarrier layers 31.

For example, the light emitting layer 30 may have a single quantum well(SQW) structure. In such a case, the light emitting layer 30 includestwo barrier layers 31 and the well layer 32 provided between the barrierlayers 31. For example, the light emitting layer 30 may have a multiplequantum well (MQW) structure. In such a case, the light emitting layer30 includes three or more barrier layers 31 and the well layers 32provided between the barrier layers 31.

In the example illustrated in FIG. 4, the light emitting layer 30includes n+1 barrier layers 31 and n well layers 32 (where n is aninteger not less than 1). The (i+1)th barrier layer BL(i+1) is disposedbetween the second semiconductor layer 20 and the ith barrier layer BLi(where i is an integer not less than 1 and not more than n−1). The(i+1)th well layer WL(i+1) is disposed between the ith well layer WLiand the second semiconductor layer 20. The 1st barrier layer BL1 isprovided between the first semiconductor layer 10 (in this example, themultilayered film body 40) and the 1st well layer WL1. The nth welllayer WLn is provided between the nth barrier layer BLn and the (n+1)thbarrier layer BL(n+1). The (n+1)th barrier layer BL(n+1) is providedbetween the nth well layer WLn and the second semiconductor layer 20.

The well layer 32 includes a nitride semiconductor that includes a groupIII element and a group V element. For example, the well layer 32includes a nitride semiconductor that includes indium (In) and gallium(Ga). The well layer 32 includes, for example, In_(xs)Ga_(1-xs)N(0.05≦xs≦0.5). The peak wavelength of the light emitted from the lightemitting layer 30 is, for example, not less than 400 nanometers (nm) andnot more than 650 nm.

The barrier layer 31 includes a nitride semiconductor that includes agroup III element and a group V element. The bandgap energy of thebarrier layer 31 is greater than the bandgap energy of the well layer32. In the case where the barrier layer 31 includes In, thecompositional proportion of In in the group III element of the barrierlayer 31 is lower than the compositional proportion of In in the groupIII element of the well layer 32 (the In compositional proportion xsrecited above). Thereby, the bandgap energy of the well layer 32 is lessthan the bandgap energy of the barrier layer 31.

The multilayered film body 40 includes multiple first films (notillustrated) stacked along the Z-axis and a second film provided betweenthe first films. In other words, the multilayered film body 40 includesthe multiple first films and the multiple second films stackedalternately in the Z-axis direction. The first film includes, forexample, GaN; and the second film includes, for example, InGaN.

As illustrated in FIG. 3, an unevenness (a substrate unevenness 51) isprovided in the substrate major surface 50 a of the substrate 50. Anunevenness (an unevenness 61) is formed in the lower surface of thesemiconductor structural body 10 s (the first major surface 60 a of thefirst semiconductor layer 10) by forming the first semiconductor layer10 on the substrate major surface 50 a. The configuration of theunevenness 61 conforms to the configuration of the substrate unevenness51.

For example, the substrate unevenness 51 of the substrate 50 has asubstrate protrusion 51 p, a substrate side portion 51 s, and asubstrate recess 51 d. The substrate protrusion 51 p is a portion thatprotrudes relatively more than does the substrate recess 51 d. Thesubstrate recess 51 d is a portion that recedes relatively more thandoes the substrate protrusion 51 p. The substrate side portion 51 s is aportion between the substrate protrusion 51 p and the substrate recess51 d. The substrate side portion 51 s is, for example, a side surface ofthe substrate unevenness 51. The substrate side portion 51 s has, forexample, a tilted surface.

On the other hand, the unevenness 61 of the first semiconductor layer 10has a recess 61 d, a side portion 61 s, and a protrusion 61 p. Therecess 61 d is a portion that recedes relatively more than does theprotrusion 61 p. The protrusion 61 p is a portion that protrudesrelatively more than does the recess 61 d. The side portion 61 s is aportion between the recess 61 d and the protrusion 61 p. The sideportion 61 s is, for example, a side surface of the unevenness 61. Theside portion 61 s has, for example, a tilted surface.

The substrate protrusion 51 p faces the recess 61 d of the firstsemiconductor layer 10 along the Z-axis. The substrate recess 51 d facesthe protrusion 61 p of the first semiconductor layer 10 along theZ-axis. The substrate side portion 51 s faces the side portion 61 s ofthe first semiconductor layer 10.

For example, multiple substrate protrusions 51 p are formed on a flatmajor surface of a base body used to form the substrate 50. In such acase, for example, a continuous substrate recess 51 d is made in themajor surface of the base body. Or, for example, multiple substraterecesses 51 d are made on the flat major surface of the base body usedto form the substrate 50. In such a case, for example, a continuoussubstrate protrusion 51 p is formed in the major surface of the basebody. The multiple substrate protrusions 51 p or the multiple substraterecesses 51 d provided in the substrate major surface 50 a are calledmultiple substrate structural bodies.

For example, in the case where multiple recesses 61 d are provided onthe flat surface of the first semiconductor layer 10, a continuousprotrusion 61 p is provided on the surface of the first semiconductorlayer 10. Or, for example, in the case where multiple protrusions 61 pare provided on the flat surface of the first semiconductor layer 10, acontinuous recess 61 d is provided on the surface of the firstsemiconductor layer 10. The multiple recesses 61 d or the multipleprotrusions 61 p provided in the first major surface 60 a are calledmultiple structural bodies.

Examples of the substrate structural body and the structural body willnow be described.

FIG. 1 is a cross-sectional view corresponding to the cross sectionalong line A1-A2 of FIG. 2A and the cross section along line A3-A4 ofFIG. 2B. The cross section along line A1-A2 of FIG. 2A matches the crosssection along line A3-A4 of FIG. 2B. FIG. 2A illustrates substratestructural bodies Sa provided in the substrate major surface 50 a of thesubstrate 50. FIG. 2B illustrates structural bodies Sb provided in thefirst major surface 60 a of the first semiconductor layer 10.

As illustrated in FIG. 1 and FIG. 2A, the multiple substrate structuralbodies Sa are provided on the substrate major surface 50 a of thesubstrate 50. In this example, each of the multiple substrate structuralbodies Sa is the substrate protrusion 51 p provided on the substratemajor surface 50 a. In such a case, a portion of the substrate recess 51d is provided between the multiple substrate structural bodies Sa. Theembodiment is not limited thereto. As described below, each of themultiple substrate structural bodies Sa may be the substrate recess 51d. Hereinbelow, the case is described where the substrate structuralbody Sa is the substrate protrusion 51 p.

As illustrated in FIG. 1 and FIG. 2B, the multiple structural bodies Sbare provided on the first major surface 60 a of the first semiconductorlayer 10 (the semiconductor structural body 10 s). In this example, eachof the multiple structural bodies Sb is the recess 61 d provided on thefirst major surface 60 a. In such a case, a portion of the protrusion 61p is provided between the multiple structural bodies Sb.

In this example, the planar configuration of the substrate protrusion 51p is a circle and the planar configuration of the recess 61 d is acircle when viewed along the Z-axis. In other words, in this example,the multiple substrate structural bodies Sa are provided on thesubstrate major surface 50 a of the substrate 50 in circular-conictrapezoidal configurations. The embodiment is not limited thereto. Theplanar configuration of the substrate protrusion 51 p and the planarconfiguration of the recess 61 d are arbitrary.

As illustrated in FIG. 2A and FIG. 2B, in this example, the multiplesubstrate structural bodies Sa and the multiple structural bodies Sb aredisposed respectively at the center and the six corners of a regularhexagon when viewed along the Z-axis. In other words, the multiplesubstrate protrusions 51 p are disposed respectively at the center andthe six corners of the regular hexagon. Also, the multiple recesses 61 dof the first semiconductor layer 10 are disposed respectively at thecenter and the six corners of the regular hexagon. However, thedisposition of the multiple substrate structural bodies Sa and thedisposition of the multiple structural bodies Sb are arbitrary.

Thus, in addition to the first semiconductor layer 10, the secondsemiconductor layer 20, and the light emitting layer 30, thesemiconductor light emitting device 60 may further include the substrate50 contacting the first major surface 10 a. The substrate 50 includesthe multiple substrate structural bodies Sa conforming to the multiplestructural bodies Sb.

As illustrated in FIG. 1 and FIG. 2A, the configuration of a firstsubstrate structural body Sa1 of the multiple substrate structuralbodies Sa when viewed along the Z-axis has a centroid Ca1 (a firstcentroid). The configuration of a second substrate structural body Sa2of the multiple substrate structural bodies Sa nearest the firstsubstrate structural body Sa1 when viewed along the Z-axis has acentroid Ca2 (a second centroid). The first centroid aligns with thesecond centroid along the second axis perpendicular to the first axis.The centroid Ca1 of the configuration of the first substrate structuralbody Sa1 of the multiple substrate structural bodies Sa when viewedalong the Z-axis aligns along the second axis with the centroid Ca2 ofthe configuration of the second substrate structural body Sa2 of themultiple substrate structural bodies Sa nearest the first substratestructural body Sa1 when viewed along the Z-axis. In this example, thesecond axis is set to be parallel to the X-axis.

The distance along the second axis (in this example, the X-axis) betweenthe centroid Ca1 of the first substrate structural body Sa1 and thecentroid Ca2 of the second substrate structural body Sa2 is taken as aspacing Ta. The spacing Ta corresponds to the disposition pitch of themultiple substrate structural bodies Sa.

The width along the second axis (in this example, the X-axis) of asubstrate apical portion 51 t of the substrate protrusion 51 p is takenas a substrate protrusion width ra. The width of the substrate recess 51d along the second axis is taken as a substrate recess width Ra. Thewidth of one substrate side portion 51 s along the second axis is(Ta−Ra−ra)/2.

The height of the substrate protrusion 51 p is taken as a substrateprotrusion height ha. The substrate protrusion height ha is the distancealong the Z-axis between the Z-axis position of the substrate protrusion51 p and the Z-axis position of the substrate recess 51 d.

On the other hand, as illustrated in FIG. 1 and FIG. 2B, theconfiguration of a first structural body Sb1 of the multiple structuralbodies Sb of the first semiconductor layer 10 when viewed along theZ-axis aligns has a centroid Cb1 (a first centroid). The configurationof a second structural body Sb2 of the multiple structural bodies Sbnearest the first structural body Sb1 when viewed along the Z-axis has acentroid Cb2 (a second centroid). The first centroid aligns with thesecond centroid along a second axis perpendicular to the first axis. Thefirst centroid aligns with the second centroid along a second axisperpendicular to the first axis. The centroid Cb1 of the configurationof the first structural body Sb1 of the multiple structural bodies Sb ofthe first semiconductor layer 10 when viewed along the Z-axis alignsalong the second axis (in this example, along the X-axis) with thecentroid Cb2 of the configuration of the second structural body Sb2 ofthe multiple structural bodies Sb nearest the first structural body Sb1when viewed along the Z-axis.

The distance along the second axis between the centroid Cb1 of the firststructural body Sb1 and the centroid Cb2 of the second structural bodySb2 is taken as a spacing Tb. The spacing Tb corresponds to thedisposition pitch of the multiple structural bodies Sb.

The width of a bottom portion 61 b of the recess 61 d of the firstsemiconductor layer 10 along the second axis is taken as a recess widthrb. The width of the protrusion 61 p along the second axis is taken as aprotrusion width Rb. The width of one side portion 61 s along the secondaxis is (Tb−Rb−rb)/2.

The depth of the recess 61 d of the first semiconductor layer 10 istaken as a recess depth hb. The recess depth hb is the distance alongthe Z-axis between the Z-axis position of the recess 61 d and the Z-axisposition of the protrusion 61 p.

The spacing Tb is substantially the same as the spacing Ta. The recesswidth rb is substantially the same as the substrate protrusion width ra.The protrusion width Rb is substantially the same as the substraterecess width Ra. The recess depth hb is substantially the same as thesubstrate protrusion height ha.

The substrate protrusion height ha and the recess depth hb may be, forexample, not less than about 0.5 micrometers (μm) and not more thanabout 3 μm. The substrate protrusion width ra and the recess width rbmay be, for example, not less than 0.5 μm and not more than 4.0 μm. Thesubstrate recess width Ra and the protrusion width Rb may be, forexample, not less than 0.5 μm and not more than 4.0 μm.

In the semiconductor light emitting device 110 according to theembodiment, the substrate protrusion height ha, the substrate protrusionwidth ra, and the substrate recess width Ra recited above satisfy therelationships of the following first formula and second formula:

ra/(2·ha)≦0.7  (1)

ra/Ra<1  (2)

The recess depth hb, the recess width rb, and the protrusion width Rbsatisfy the relationships of the following third formula and fourthformula:

rb/(2·hb)≦0.7  (3)

rb/Rb<1  (4)

Thereby, a semiconductor light emitting device having a high efficiencycan be provided. In other words, as described below, the occurrence ofpits is suppressed by satisfying the relationships recited above.Thereby, a semiconductor light emitting device having high lightextraction efficiency and high crystallinity is obtained.

Experimental results that formed the basis for discovering theconfiguration of the embodiment recited above will now be described.

In the substrate 50 used in this experiment as illustrated in FIG. 1 andFIG. 2A, multiple substrate protrusions 51 p were provided as themultiple substrate structural bodies Sa in the substrate major surface50 a of the substrate 50.

A photoresist was formed on the substrate major surface 50 a of thesubstrate 50, which was made of c-plane sapphire. This photoresist had arepeating pattern of circles corresponding to the pattern of thesubstrate protrusions 51 p illustrated in FIG. 2A. Subsequently, theregion of the substrate major surface 50 a not covered with thephotoresist was etched using RIE (Reactive Ion Etching). Thereby, themultiple substrate structural bodies Sa were formed in circular-conictrapezoidal configurations on the substrate major surface 50 a.

In this experiment, two types of the substrates 50 were constructed bychanging the opening pattern of the photomask (and the etchingconditions).

For the substrate 50 of a first sample, ra=2.3 μm, Ra=1.5 μm, ha=1.0 μm,and Ta=5 μm. For the substrate 50 of a second sample, ra=1.0 μm, Ra=2.3μm, ha=1.0 μm, and Ta=5 μm. An undoped GaN layer was formed on each ofthese substrates 50. This layer corresponds to the foundation layer 60which is a portion of the first semiconductor layer 10.

Specifically, the substrates 50 of the first sample and the secondsample were processed by organic cleaning and acid cleaning; and thesubstrates 50 were placed inside the reaction chamber of an MOCVDsystem. Then, a GaN layer used to form the buffer layer 55 was formedusing trimethylgallium (TMGa) and ammonia (NH₃). The thickness of thebuffer layer 55 was about 30 nm.

Then, an undoped GaN layer used to form a portion of the foundationlayer 60 was formed using TMGa and ammonia in an atmosphere includingnitrogen and hydrogen at 1120° C.

The growth conditions of the GaN layers used to form the buffer layer 55and the portion of the foundation layer 60 were the same for the firstsample and the second sample. The growth process (formation state), thepits, the dislocations, and the like of the GaN layers of such sampleswere evaluated. In this experiment, samples of different GaN layerthicknesses were evaluated by changing the growth time of the GaN layerused to form the portion of the foundation layer 60.

FIG. 5A to FIG. 5F are electron microscope images and schematic viewsillustrating states of the crystal layers of the first sample and thesecond sample.

FIG. 6 is an electron microscope photograph illustrating the state ofthe crystal layer of the second sample.

FIG. 5A to FIG. 5C are scanning electron microscope (SEM) images. TheseSEM images are taken from a direction substantially perpendicular to thesubstrate major surface 50 a of the substrate 50. FIG. 5A corresponds toa growth time of 20 minutes for the GaN layer of the substrate 50 of thefirst sample. In other words, FIG. 5A corresponds to the averagethickness of the GaN layer being about 1.0 μm. FIG. 5B corresponds to aformation time of 30 minutes for the GaN layer of the substrate 50 ofthe first sample. In other words, FIG. 5B corresponds to the averagethickness of the GaN layer being about 1.5 μm. FIG. 5C and FIG. 6correspond to a formation time of 20 minutes for the GaN layer of thesubstrate 50 of the second sample recited above. In other words, FIG. 5Cand FIG. 6 correspond to the average thickness of the GaN layer beingabout 1.0 μm.

FIG. 5D to FIG. 5F are schematic plan views illustrating the states (thegrowth states) of the crystal layers. These drawings are drawn based onthe SEM images of FIG. 5A to FIG. 5C, respectively.

FIG. 6 is a SEM image of the sample illustrated in FIG. 5C taken from adirection oblique to the substrate major surface 50 a.

In the first sample spl-1 as illustrated in FIG. 5A and FIG. 5D, acrystal layer Dg (a GaN layer) grew on the substrate recess 51 d; and acrystal layer Pg (a GaN layer) grew on the substrate protrusion 51 p.Thus, for the first sample spl-1, the crystal of the GaN used to formthe foundation layer 60 grew on both the substrate recess 51 d and thesubstrate protrusion 51 p in the initial stage of the formation of thefoundation layer 60.

As illustrated in FIG. 5D, the angles of the oblique surfaces of thecrystal layer Dg grown on the substrate recess 51 d (the angles in aplane parallel to the substrate major surface 50 a) were different fromthe angles of the oblique surfaces of the crystal layer Pg grown on thesubstrate protrusion 51 p (the angles in the plane parallel to thesubstrate major surface 50 a). In other words, the configurations of thehexagons of the crystals differed by 90 degrees around the Z-axis.

As illustrated in FIG. 5B and FIG. 5E, when the GaN layer was grownfurther and the thickness of the GaN layer was increased, the crystallayer Dg grown from the substrate recess 51 d combined with the crystallayer Pg grown from the substrate protrusion 51 p. Pits Pp were observedin the GaN layer. The pits Pp occurred at the portions where the obliquesurfaces of the crystal layer Dg grown from the substrate recess 51 dcombined with the oblique surfaces of the crystal layer Pg grown fromthe substrate protrusion 51 p.

On the other hand, in the substrate 50 of the second sample spl-2 asillustrated in FIG. 5C and FIG. 5F, the crystal layer Dg grew on thesubstrate recess 51 d; but a GaN layer substantially did not grow on thesubstrate protrusion 51 p.

It can also be seen from the SEM image of the GaN layer of the secondsample spl-2 taken from the oblique direction as illustrated in FIG. 6that the GaN layer substantially did not grow on the substrateprotrusion 51 p.

As the formation time of the GaN layer continued for the second samplespl-2, the crystal layer Dg grown from the substrate recess 51 dcombined with itself; and a flat GaN layer having no pits Pp wasobtained.

Thus, it was found that the state of the crystal layer (the GaN layer)formed on the unevenness provided in the substrate 50 changes accordingto the configuration of the unevenness.

The experimental results recited above relating to the growth states ofthe GaN layers of the first sample spl-1 and the second sample spl-2 canbe described as follows.

FIG. 7A to FIG. 7D are schematic cross-sectional views illustratingstates of the crystal layers of the first sample and the second sample.

FIG. 7A to FIG. 7C correspond to the states of FIG. 5A to FIG. 5C,respectively. FIG. 7D corresponds to the state (e.g., a formation timeof the GaN layer of 30 minutes) after the state of FIG. 7C.

As illustrated in FIG. 7A, the crystal layer Dg grown from the substraterecess 51 d of the first sample spl-1 has an upper surface and obliquesurfaces. The upper surface of the crystal layer Dg is, for example, a(0001) plane parallel to the substrate major surface 50 a. The obliquesurfaces of the crystal layer Dg are crystal planes equivalent to a(11-22) plane and a (11-22) plane.

The crystal layer Pg grown from the substrate protrusion 51 p also hasan upper surface and oblique surfaces. In such a case as well, the uppersurface of the crystal layer Pg is, for example, the (0001) planeparallel to the substrate major surface 50 a. On the other hand, theoblique surfaces of the crystal layer Pg are crystal planes equivalentto a (10-11) plane and a (10-11) plane.

Thus, the plane orientations of the oblique surfaces of the crystallayer Dg grown from the substrate recess 51 d are different from theplane orientations of the oblique surfaces of the crystal layer Pg grownfrom the substrate protrusion 51 p. In other words, the oblique surfacesof the crystal layer Dg grown from the substrate recess 51 d are rotated90 degrees around the Z-axis from the oblique surfaces of the crystallayer Pg grown from the substrate protrusion 51 p. This state isobserved in FIG. 5A.

Therefore, as illustrated in FIG. 5D, the configuration of the hexagonformed by these oblique surfaces differs by 90 degrees between thecrystal layer Dg grown from the substrate recess 51 d and the crystallayer Pg grown from the substrate protrusion 51 p when viewed along theZ-axis.

Then, when the GaN layer is grown further as illustrated in FIG. 7B, thecrystal layer Dg grown from the substrate recess 51 d combines with thecrystal layer Pg grown from the substrate protrusion 51 p. At this time,the pits Pp occur at the portions where these oblique surfaces combinebecause the plane orientations are different between the obliquesurfaces of the crystal layer Dg (e.g., the (11-22) planes) and theoblique surfaces of the crystal layer Pg (e.g., the (10-11) planes). Thepits Pp extend along the crystal planes equivalent to the (1-101) planeand the (1-101) plane of the GaN layer. In other words, the pits Ppoccur parallel to the <11-20> axis (i.e., the a-axis) of the GaN layer.Thus, when the foundation layer 60 is formed by increasing the thicknessof the GaN layer in the first sample spl-1, the pits Pp remain inportions; and a flat foundation layer 60 is not obtained.

On the other hand, in the second sample spl-2 as illustrated in FIG. 7C,the crystal layer Dg grows on the substrate recess 51 d; but a GaN layersubstantially does not grow on the substrate protrusion 51 p. In otherwords, mainly a GaN layer having oblique surfaces of the (11-22) planegrows.

Therefore, when the thickness of the GaN layer is increased asillustrated in FIG. 7D, the substrate protrusion 51 p is covered withthe GaN layer (the crystal layer Dg). Therefore, the pits Pp do notoccur easily. Thus, a flat GaN layer is formed in which the occurrenceof the pits Pp on the substrate 50 of the second sample spl-2 issuppressed.

It was also seen that the GaN layer had irregular growth from theoblique surface (the substrate side portion 51 s) of the substrateunevenness 51 in the first sample spl-1.

FIG. 8 is a cross section scanning electron microscope photographillustrating the state of the crystal layer of the first sample.

This photograph is a cross section transmission electron microscope(TEM) image of the GaN layer (corresponding to the foundation layer 60)grown on the substrate 50 of the first sample spl-1.

In the GaN layer (the foundation layer 60) grown on the substrate 50 ofthe first sample spl-1 as illustrated in FIG. 8, other than the pits Pp,an oblique surface irregular growth layer Sg grown from the obliquesurface (the substrate side portion 51 s) of the substrate unevenness 51was observed. Many dislocations Dl also were observed in this sample(the black lines in the image of FIG. 8 corresponding to thedislocations Dl). The pits Pp, the oblique surface irregular growthlayer Sg, and the dislocations Dl reduce the crystallinity of the n-sidecontact layer 11, the light emitting layer 30, and the secondsemiconductor layer 20 formed on the foundation layer 60 and, as aresult, reduce the efficiency of the semiconductor light emittingdevice.

On the other hand, the oblique surface irregular growth layer Sg thatgrows from the oblique surface (the substrate side portion 51 s) of thesubstrate unevenness 51 was not observed for the GaN layer grown on thesubstrate 50 of the second sample spl-2. Also, the number of thedislocations Dl was extremely low.

Thus, the inventor experimentally discovered that the state of the pitsPp, the oblique surface irregular growth layer Sg, and the dislocationsDl occurring in the GaN layer grown on the substrate unevenness 51provided in the substrate 50 change according to the configuration (therelationship between the dimensions of the substrate protrusion 51 p andthe dimensions of the substrate recess 51 d) of the substrate unevenness51.

Based on this knowledge, the inventor further constructed the substrates50 having multiple substrate structural bodies Sa of various dimensionsand various configurations. In other words, the multiple substratestructural bodies Sa having various dimensions and variousconfigurations were formed by patterning a base body used to form thesubstrate 50 by changing the opening pattern of the photomask and theetching conditions.

FIG. 9 is a table illustrating the configurations of the substrates andthe characteristics of the crystal layers grown on the substrates usedin the experiment.

The first sample spl-1 and the second sample spl-2 described above alsoare illustrated in this table.

In this experiment as illustrated in FIG. 9, the substrate 50 having thesubstrate unevenness 51 also was constructed for a third sample spl-3 toa seventh sample spl-7. The table illustrates the substrate protrusionwidth ra (i.e., the recess width rb), the substrate recess width Ra(i.e., the protrusion width Rb), the substrate protrusion height ha(i.e., the recess depth hb), and the spacing Ta (i.e., the spacing Tb)of the samples. The buffer layer 55 (the GaN layer) was formed on eachof these substrates 50; and an undoped GaN layer used to form thefoundation layer 60 was formed on the buffer layer 55. The formationconditions of these layers were the same as those described in regard tothe first sample spl-1 and the second sample spl-2.

Then, SEM images were taken for the GaN layers that were obtained; andthe growth states of the GaN layers were evaluated. In particular,attention was given to the crystal layer Pg grown from the substrateprotrusion 51 p and the oblique surface irregular growth layer Sg grownfrom the oblique surface of the substrate unevenness 51 (the substrateside portion 51 s) in the initial growth of the GaN layer.

FIG. 9 illustrates the evaluation results of the growth/nongrowth of thecrystal layer Pg grown from the substrate protrusion 51 p and thegrowth/nongrowth of the oblique surface irregular growth layer Sg.

The crystal layer Pg grown from the substrate protrusion 51 p wasobserved for the first sample spl-1 and the fifth sample spl-5 to theseventh sample spl-7 as illustrated in FIG. 9. Conversely, the crystallayer Pg grown from the substrate protrusion 51 p was not observed forthe second sample spl-2 to the fourth sample spl-4.

It is conceivable that whether or not the GaN layer grows from thesubstrate protrusion 51 p depends on the relative relationship betweenthe width of the substrate protrusion 51 p (the substrate protrusionwidth ra) and the height of the substrate protrusion 51 p (the substrateprotrusion height ha). In other words, it is conceivable that the GaNlayer does not grow easily on the substrate protrusion 51 p when thewidth of the substrate protrusion 51 p is sufficiently less than theheight of the substrate protrusion 51 p. The relationship between ra/2and ha was investigated.

As illustrated in FIG. 9, the crystal layer Pg does not grow on thesubstrate protrusion 51 p when ra/(2·ha) is 0.5. On the other hand, thecrystal layer Pg grows on the substrate protrusion 51 p when ra/(2·ha)is 1.15. It was found that there are cases where the crystal layer Pggrows and does not grow on the substrate protrusion 51 p when ra/(2·ha)is 0.65 and 0.70.

Further, it is conceivable that whether or not the GaN layer grows fromthe substrate protrusion 51 p depends on the relative relationshipbetween the width of the substrate protrusion 51 p (the substrateprotrusion width ra) and the width of the substrate recess 51 d (thesubstrate recess width Ra). In other words, it is conceivable that theGaN layer grows less easily on the substrate protrusion 51 p because thesource-material gas is preferentially supplied to the substrate recess51 d by vapor phase diffusion and surface diffusion when the width ofthe substrate protrusion 51 p (the substrate protrusion width ra) issufficiently narrow.

As illustrated in FIG. 9, ra/Ra is less than 1 for the second samplespl-2 to the fourth sample spl-4. Also, ra/Ra is not less than 1 in thefirst sample spl-1 and the fifth sample spl-5 to the seventh samplespl-7. Therefore, it can be seen that the growth of the crystal layer Pgon the substrate protrusion 51 p is suppressed when ra/Ra is less than1, that is, when the width of the substrate protrusion 51 p is narrowerthan the width of the substrate recess 51 d.

From the description recited above, in the semiconductor light emittingdevice 110 according to the embodiment, the substrate protrusion heightha, the substrate protrusion width ra, and the substrate recess width Raare set to satisfy the relationships

ra/(2·ha)≦0.7  (1)

ra/Ra<1  (2)

The recess depth hb, the recess width rb, and the protrusion width Rbare set to satisfy the relationships

rb/(2·hb)≦0.7  (3)

rb/Rb<1  (4)

Thereby, the growth of the crystal layer Pg on the substrate protrusion51 p is suppressed. Also, the occurrence of the pits Pp as the crystallayer Pg grows is suppressed. Thereby, a semiconductor light emittingdevice having a high efficiency can be provided. In other words, asemiconductor light emitting device that realizes high light extractionefficiency and high crystallinity is obtained.

It is more desirable for ra/(2·ha) to be not less than 0.4 and not morethan 0.7.

It is more desirable for ra/Ra to be not less than 0.25 and not morethan 0.6.

It is more desirable for rb/(2·hb) to be not less than 0.4 and not morethan 0.7.

It is more desirable for rb/Rb to be not less than 0.25 and not morethan 0.6.

In the case where the pits Pp exist, there are cases where current leaksthrough the pits Pp and the reliability of the semiconductor lightemitting device decreases. In the embodiment, high reliability isobtained in addition to high efficiency because the occurrence of thepits Pp is suppressed.

It is conceivable that whether or not the GaN layer grows from thesubstrate protrusion 51 p depends also on the relative relationshipbetween the surface area of the substrate protrusion 51 p and thesurface area of the substrate recess 51 d in the substrate major surface50 a. In other words, it is conceivable that the GaN layer does not groweasily on the substrate protrusion 51 p when the surface area of thesubstrate protrusion 51 p is sufficiently small with respect to thesurface area of the substrate recess 51 d. Here, the total of thesurface area of the substrate protrusion 51 p, the surface area of thesubstrate recess 51 d, and the surface area of the substrate sideportion 51 s is taken to be the surface area of the substrate majorsurface 50 a when viewed along the Z-axis.

FIG. 9 illustrates a ratio Sr of the total surface area of the substrateapical portion 51 t per unit surface area of the substrate major surface50 a to the total surface area of the substrate recess 51 d per the unitsurface area for the first sample spl-1 to the seventh sample spl-7. Itcan be seen from FIG. 9 that the ratio Sr is not less than 0.17 for thefirst sample spl-1 and the fifth sample spl-5 to the seventh samplespl-7. The ratio Sr is less than 0.17 for the second sample spl-2 to thefourth sample spl-4. Therefore, it is desirable for the ratio Sr to beless than 0.17, and more desirably, not more than 0.11. Thereby, thegrowth of the crystal layer Pg on the substrate protrusion 51 p issuppressed; and the occurrence of the pits Pp is drastically suppressed.

In the first semiconductor layer 10 (e.g., the foundation layer 60), itis desirable for the ratio (corresponding to Sr recited above) of thetotal surface area of the bottom portion 61 b of the recess 61 d perunit surface area of the first major surface 60 a to the total surfacearea of the protrusion 61 p per the unit surface area to be less than0.17, and more desirably, not more than 0.11.

As illustrated in FIG. 9, the oblique surface irregular growth layer Sgwas observed for the first sample spl-1, the fifth sample spl-5, and theseventh sample spl-7. On the other hand, the oblique surface irregulargrowth layer Sg was not observed for the second sample spl-2 to thefourth sample spl-4 and the sixth sample spl-6.

It is conceivable that whether or not the oblique surface irregulargrowth layer Sg forms depends on the configuration of the tilted surfaceof the substrate side portion 51 s. In other words, it is conceivablethat the occurrence of the oblique surface irregular growth layer Sg issuppressed when the tilt of the oblique surface is gradual.

The relationship between the width of the substrate side portion 51 sand the substrate protrusion height ha of the substrate protrusion 51 pwas investigated regarding the tilt of the oblique surface. The width ofone substrate side portion 51 s is (Ta−Ra−ra)/2.

FIG. 9 illustrates the values of ha/(Ta−Ra−ra). It can be seen from FIG.9 that the oblique surface irregular growth layer Sg was not observedwhen ha/(Ta−Ra−ra) was not more than 0.59.

It is considered that the oblique surface irregular growth layer Sg isthe GaN layer growing from the (11-23) plane (i.e., the n-plane) of thesapphire substrate. The (11-23) plane (i.e., the n-plane) of thesapphire substrate is a major crystal plane of the oblique surface (thesubstrate side portion 51 s) in the case where ha/(Ta−Ra−ra) is 0.65 to0.8. In such a case, the oblique surface irregular growth layer Sg formseasily. Accordingly, it is conceivable that the growth of the GaN layeron the oblique surface (the substrate side portion 51 s) is suppressedby ha/(Ta−Ra−ra) being not more than 0.6, that is, by suppressing theformation of the (11-23) plane of the sapphire substrate. This matchesthe experimental results illustrated in FIG. 9.

Thus, in the substrate 50, it is favorable for ha/(Ta−Ra−ra) to be notmore than 0.6. In other words, it is favorable for hb/(Tb−Rb−rb) of thefirst semiconductor layer 10 (the foundation layer 60) to be not morethan 0.6. Thereby, the formation of the oblique surface irregular growthlayer Sg is suppressed; and a crystal having a low dislocation densityand high quality is obtained. Thereby, a high efficiency is obtained. Itis more favorable for ha/(Ta−Ra−ra) to be not more than 0.5. It is morefavorable for hb/(Tb−Rb−rb) of the first semiconductor layer 10 (thefoundation layer 60) to be not more than 0.5.

ha/(Ta−Ra−ra) and hb/(Tb−Rb−rb) are set to be not less than 0. In otherwords, the oblique surfaces of the substrate unevenness 51 have forwardtapers.

In the embodiment, it is favorable for the substrate protrusion heightha and the recess depth hb of the recess 61 d of the first semiconductorlayer 10 to be larger than the peak wavelength of the light emitted fromthe light emitting layer 30. Thereby, for example, the light extractionefficiency can be increased due to the diffraction effect of the light.

The surface flatness degrades in the case where the substrate protrusionheight ha and the recess depth hb are too large. It is favorable for thesubstrate protrusion height ha and the recess depth hb to be, forexample, not more than the substrate recess width Ra (the protrusionwidth Rb). Thereby, high surface flatness is obtained.

In the embodiment, for example, the substrate apical portion 51 t of thesubstrate protrusion 51 p has a portion parallel to the substrate majorsurface 50 a. The recess 61 d of the first semiconductor layer 10 has aportion parallel to the first major surface 60 a.

For example, there are cases where the circumferential edge portion ofthe substrate protrusion 51 p is rounded when the substrate 50 is cut bya plane including the Z-axis. Also, there are cases where thecircumferential edge portion of the substrate recess 51 d is rounded.

In such cases, for example, the substrate protrusion 51 p, the substraterecess 51 d, and the substrate side portion 51 s can be defined asfollows for convenience. Namely, the substrate protrusion 51 p may betaken to be, for example, the portion from the most protruding portionof the substrate unevenness 51 to the distance of 10% of the substrateprotrusion height ha from the most protruding portion of the substrateunevenness 51. The substrate recess 51 d may be taken to be, forexample, the portion from the most receding portion of the substrateunevenness 51 to the distance of 10% of the substrate protrusion heightha from the most receding portion of the substrate unevenness 51. Thesubstrate side portion 51 s may be taken to be the portion of thesubstrate unevenness 51 other than the substrate protrusion 51 p and thesubstrate recess 51 d (the portion of 80% of the substrate protrusionheight ha).

Similarly, the recess 61 d, the protrusion 61 p, and the side portion 61s of the first semiconductor layer 10 can be defined as follows forconvenience. Namely, the recess 61 d may be taken to be, for example,the portion from the most receding portion of the unevenness 61 to thedistance of 10% of the recess depth hb from the most receding portion ofthe unevenness 61. The protrusion 61 p may be taken to be, for example,the portion from the most protruding portion of the unevenness 61 to thedistance of 10% of the recess depth hb from the most protruding portionof the unevenness 61. The side portion 61 s may be taken to be theportion of the unevenness 61 other than the protrusion 61 p and therecess 61 d (the portion of 80% of the recess depth hb).

Example

A semiconductor light emitting device according to an example of theembodiment will now be described. The semiconductor light emittingdevice 111 of the example had the configuration described in regard tothe semiconductor light emitting device 110 as illustrated in FIG. 1,FIG. 2A, FIG. 2B, FIG. 3, and FIG. 4. The semiconductor light emittingdevice 111 was formed on the substrate 50 of the second sample spl-2.

The method for manufacturing the semiconductor light emitting device 111will now be described. This manufacturing method is one example of themethod for manufacturing the semiconductor light emitting device of theembodiment.

The substrate 50 having the configuration of the second sample spl-2 wasprocessed by organic cleaning and acid cleaning. A GaN layer used toform the buffer layer 55 was formed using TMGa and NH₃ in an MOCVDapparatus. The thickness of the buffer layer 55 was, for example, about30 nm.

Then, an undoped GaN layer used to form the foundation layer 60 wasformed using TMGa and ammonia in an atmosphere including nitrogen andhydrogen at 1120° C. The thickness of the foundation layer 60 was, forexample, about 3 μm.

An n-type GaN layer used to form the n-side contact layer 11 was formedby adding silane (SiH₄) as an impurity source-material gas. Thethickness of the n-side contact layer 11 was, for example, about 4 μm.

The multilayered film body 40 was formed on the n-side contact layer 11.Specifically, an undoped GaN film used to form a first film was formedusing TMGa and ammonia in a nitrogen atmosphere. The growth temperatureof the first film was, for example, about 800° C. The thickness of thefirst film was, for example, about 3 nm. An undoped In_(0.07)Ga_(0.93)Nfilm used to form a second film was formed on the first film by addingtrimethylindium (TMIn). The formation temperature of the second filmwas, for example, about 800° C. The thickness of the second film was,for example, about 1 nm. The formation of the first film and theformation of the second film was repeated a total of 20 times. Then, thefirst film was formed on the final second film. Thereby, themultilayered film body 40 was formed.

Then, an undoped GaN layer used to form the barrier layer 31 was formedusing TMGa and ammonia in a nitrogen atmosphere with the temperature ofthe substrate 50 at, for example, about 850° C. The thickness of thebarrier layer 31 was, for example, about 5 nm. Continuing, an undopedIn_(0.15)Ga_(0.85)N layer used to form the well layer 32 was formedusing TMGa, TMIn, and ammonia with the temperature of the substrate 50at, for example, about 730° C. The thickness of the well layer 32 was,for example, about 2.5 nm. Then, the light emitting layer 30 was formedby repeatedly implementing the formation of the barrier layer 31 and theformation of the well layer 32 recited above. The number of the welllayers 32 (the number of stacks) was eight.

Continuing, an AlGaN layer used to form the third p-side layer 23 wasformed using TMA trimethylaluminum (TMAl), TMGa, and ammonia and usingbis(cyclopentadienyl)magnesium (Cp₂Mg) as an impurity source material inan atmosphere including nitrogen and hydrogen at, for example, about1030° C. Then, a p-type GaN layer used to form the second p-side layer22 was formed using TMGa and ammonia; and a p-type GaN layer used toform the first p-side layer 21 was formed on the p-type GaN layer thatwas used to form the second p-side layer 22. The thickness of the thirdp-side layer 23 was, for example, 10 nm; the thickness of the secondp-side layer 22 was, for example, 80 nm; and the thickness of the firstp-side layer 21 was, for example, 10 nm. Thereby, the semiconductorstructural body 10 s was formed.

Subsequently, the temperature of the substrate 50 was reduced to roomtemperature. Then, a portion of the second semiconductor layer 20 and aportion of the light emitting layer 30 were removed by performing dryetching from the major surface of the semiconductor structural body 10 son the second semiconductor layer 20 side to reach a thickness partwaythrough the n-side contact layer 11. Thereby, a portion of the firstsemiconductor layer 10 (the n-side contact layer 11) was exposed. Thefirst electrode 70 having a stacked film of a Ti film/Pt film/Au filmwas formed on the n-side contact layer 11 that was exposed. An ITO layerused to form the second electrode 80 was formed on the first p-sidelayer 21. Thereby, the semiconductor light emitting device 111 wasformed.

Then, as a reference example, a semiconductor light emitting device 191was formed on the substrate 50 of the first sample spl-1 usingconditions similar to those of the semiconductor light emitting device111.

FIG. 10, FIG. 11A, and FIG. 11B are graphs illustrating characteristicsof the semiconductor light emitting devices of the example and thereference example.

The vertical axis of FIG. 10 is a pit density Cp; the vertical axis ofFIG. 11A is a screw dislocation density Cs; and the vertical axis ofFIG. 11B is an edge dislocation density Ce. The pit density Cp wasdetermined from SEM images. The screw dislocation density Cs and theedge dislocation density Ce were determined from TEM images.

As illustrated in FIG. 10, the pit density Cp was about 280 pits/mm² forthe semiconductor light emitting device 191 of the reference example. Incontrast, for the semiconductor light emitting device 111 of thereference example, no pits Pp were observed; and the pit density Cp was0 pits/mm².

As illustrated in FIG. 11A, although the screw dislocation density Cs ofthe semiconductor light emitting device 191 was about 5.4×10⁷/mm², thescrew dislocation density Cs of the semiconductor light emitting device111 was about 5.1×10⁷/mm². As illustrated in FIG. 11B, although the edgedislocation density Ce of the semiconductor light emitting device 191was about 4.1×10⁸/mm², the edge dislocation density Ce of thesemiconductor light emitting device 111 was about 3.2×10⁸/mm².

Thus, the pit density Cp, the screw dislocation density Cs, and the edgedislocation density Ce were lower for the semiconductor light emittingdevice 111 of the example than for the semiconductor light emittingdevice 191 of the reference example.

In the semiconductor light emitting device 111, the growth of thecrystal layer Pg from the substrate protrusion 51 p was suppressed.Thereby, the occurrence of the pits Pp was suppressed. Also, thedislocation density of the entirety decreased because dislocationssubstantially did not occur on the substrate protrusion 51 p.

In the semiconductor light emitting device 191 of the reference example,the oblique surface irregular growth layer Sg was observed; anddislocations occurred from the oblique surface irregular growth layerSg. In contrast, in the semiconductor light emitting device 111, theoblique surface irregular growth layer Sg was not observed. In thesemiconductor light emitting device 111, it is conceivable that thedislocation density decreased because the occurrence of defects in thesubstrate protrusion 51 p and the substrate side portion 51 s weresuppressed.

Measuring the light emission characteristics of the semiconductor lightemitting devices 111 and 191 showed that the light output of thesemiconductor light emitting device 111 was about 1.05 times the lightoutput of the semiconductor light emitting device 191.

FIG. 12 is a schematic cross-sectional view illustrating theconfiguration of another semiconductor light emitting device accordingto the first embodiment.

FIG. 13A and FIG. 13B are schematic plan views illustrating theconfiguration of another semiconductor light emitting device accordingto the first embodiment.

FIG. 12 is a cross-sectional view corresponding to the cross sectionalong line A1-A2 of FIG. 13A and the cross section along line A3-A4 ofFIG. 13B. The cross section along line A1-A2 of FIG. 13A matches thecross section along line A3-A4 of FIG. 13B. FIG. 13A illustrates thesubstrate structural bodies Sa provided in the substrate major surface50 a of the substrate 50. FIG. 13B illustrates the structural bodies Sbprovided in the first major surface 60 a of the first semiconductorlayer 10.

In the semiconductor light emitting device 120 according to theembodiment as illustrated in FIG. 12 and FIG. 13A, each of the multiplesubstrate structural bodies Sa is the substrate recess 51 d provided onthe substrate major surface 50 a. In such a case, a portion of thesubstrate protrusion 51 p is provided between the multiple substratestructural bodies Sa.

As illustrated in FIG. 12 and FIG. 13B, in this example, each of themultiple structural bodies Sb is the protrusion 61 p provided on thefirst major surface 60 a. In such a case, a portion of the recess 61 dis provided between the multiple structural bodies Sb.

In this example, the planar configuration of the substrate recess 51 dis a circle and the planar configuration of the protrusion 61 p is acircle when viewed along the Z-axis. In other words, in this example,the multiple substrate structural bodies Sa are provided as holes havingcircular-conic trapezoidal configurations on the substrate major surface50 a of the substrate 50. The embodiment is not limited thereto. Theplanar configuration of the substrate recess 51 d and the planarconfiguration of the protrusion 61 p are arbitrary.

As illustrated in FIG. 13A and FIG. 13B, in this example as well, themultiple substrate structural bodies Sa and the multiple structuralbodies Sb are disposed respectively at the center and the six corners ofa regular hexagon when viewed along the Z-axis. However, the dispositionof the multiple substrate structural bodies Sa and the disposition ofthe multiple structural bodies Sb are arbitrary.

As illustrated in FIG. 12 and FIG. 13A, in this example as well, thecentroid Ca1 of the configuration of the first substrate structural bodySa1 of the multiple substrate structural bodies Sa when viewed along theZ-axis aligns along the second axis with the centroid Ca2 of theconfiguration of the second substrate structural body Sa2 of themultiple substrate structural bodies Sa nearest the first substratestructural body Sa1 when viewed along the Z-axis.

In this example as well, the distance along the second axis (in thisexample, the X-axis) between the centroid Ca1 of the first substratestructural body Sa1 and the centroid Ca2 of the second substratestructural body Sa2 is taken as the spacing Ta.

The width of the substrate apical portion 51 t of the substrateprotrusion 51 p along the second axis is taken as the substrateprotrusion width ra. The width of the substrate recess 51 d along thesecond axis is taken as the substrate recess width Ra. The width of onesubstrate side portion 51 s along the second axis is (Ta−Ra−ra)/2. Theheight of the substrate protrusion 51 p is taken as the substrateprotrusion height ha.

As illustrated in FIG. 12 and FIG. 13B, the centroid Cb1 of theconfiguration of the first structural body Sb1 of the multiplestructural bodies Sb of the first semiconductor layer 10 when viewedalong the Z-axis aligns along the second axis with the centroid Cb2 ofthe configuration of the second structural body Sb2 of the multiplestructural bodies Sb nearest the first structural body Sb1 when viewedalong the Z-axis.

The distance along the second axis between the centroid Cb1 of the firststructural body Sb1 and the centroid Cb2 of the second structural bodySb2 is taken as the spacing Tb. The width of the bottom portion 61 b ofthe recess 61 d of the first semiconductor layer 10 along the secondaxis is taken as the recess width rb. The width of the protrusion 61 palong the second axis is taken as the protrusion width Rb. The width ofone side portion 61 s along the second axis is (Tb−Rb−rb)/2. The depthof the recess 61 d of the first semiconductor layer 10 is taken as therecess depth hb.

The substrate protrusion height ha and the recess depth hb may be, forexample, not less than about 0.5 μm and not more than about 3.0 μm. Thesubstrate protrusion width ra and the recess width rb may be, forexample, not less than 0.5 μm and not more than 4.0 μm. The substraterecess width Ra and the protrusion width Rb may be, for example, notless than 0.5 μm and not more than 4.0 μm.

In the semiconductor light emitting device 120 as well, the substrateprotrusion height ha, the substrate protrusion width ra, the substraterecess width Ra, the recess depth hb, the recess width rb, and theprotrusion width Rb are set to satisfy the first formula to the fourthformula recited above. Thereby, the occurrence of pits can besuppressed; and a semiconductor light emitting device having a highefficiency can be provided.

Thus, in the embodiment, the relationship between the dimensions of thesubstrate protrusion 51 p and the dimensions of the substrate recess 51d is set appropriately for the multiple substrate structural bodies Saprovided in the substrate 50. In other words, the relationship betweenthe dimensions of the recess 61 d and the dimensions of the protrusion61 p is set appropriately for the first semiconductor layer 10. Thereby,the growth of the crystal layer Pg on the substrate protrusion 51 p issuppressed. Thereby, the pit density Cp can be reduced; and thedislocation density can be reduced.

In the reference example in which the plane orientation of the substrateunevenness 51 was set to be in the prescribed direction, the suppressionof the growth of the crystal layer Pg on the substrate protrusion 51 pwas insufficient; and the decrease of the pit density Cp and thedislocation density was insufficient.

Although a reference example is conceivable in which the growth of thecrystal layer Pg on the substrate protrusion 51 p is suppressed bycontrolling the growth conditions of the nitride semiconductor layerthat is formed on the substrate major surface 50 a, the control of thegrowth conditions is difficult; the decrease of the pit density Cp isinsufficient; and it is difficult to reduce the dislocation density.

Although there are reference examples that attempt to reduce thedislocation density by suppressing the growth of the nitridesemiconductor layer at the substrate recess 51 d by controlling theconfiguration of the substrate recess 51 d, it is difficult to reducethe pit density using this method.

In contrast, in the embodiment, both the pit density Cp and thedislocation density can be reduced by the relationship between thedimensions of the substrate protrusion 51 p and the dimensions of thesubstrate recess 51 d (i.e., the relationship between the dimensions ofthe recess 61 d of the first semiconductor layer 10 and the dimensionsof the protrusion 61 p) being appropriately set.

In a reference example in which an unevenness is formed in a firstnitride semiconductor layer formed on a flat substrate and a secondnitride semiconductor layer is formed on the first nitride semiconductorlayer, the improvement effect of the light extraction efficiency issmall because the refractive index difference between the first nitridesemiconductor layer and the second nitride semiconductor layer is small.

Conversely, in the embodiment, the refractive index difference betweenthe substrate 50 and the first semiconductor layer 10 is large and theimprovement effect of the light extraction efficiency is large becausethe substrate unevenness 51 is provided in the substrate 50. Even in thecase where the substrate 50 is removed, the light extraction efficiencycan be greatly increased by the unevenness 61 being formed in the firstmajor surface 60 a of the first semiconductor layer 10.

In the embodiment, in the case where multiple substrate protrusions 51 pare provided in the substrate 50, it is favorable for the multiplesubstrate protrusions 51 p to be disposed two-dimensionally in a planeperpendicular to the Z-axis. In the case where multiple substraterecesses 51 d are provided in the substrate 50, it is favorable for themultiple substrate recesses 51 d to be disposed two-dimensionally in aplane perpendicular to the Z-axis. That is, the substrate structuralbodies 51 may be disposed in a plane parallel to the substrate majorsurface 50 a. Thereby, the effect of suppressing dislocations 65occurring from the substrate protrusion 51 p increases; the proportionof the dislocations of the first semiconductor layer 10 that areannihilated by colliding with the substrate side portion 51 s increasesdue to extension directions of the dislocations changing to horizontaldirections (directions intersecting the Z-axis); and the reductioneffect of the dislocation density increases. Further, the lightextraction efficiency can be greatly increased; and the luminousefficiency increases.

In the foundation layer 60, in the case where multiple recesses 61 d areprovided, it is favorable for the multiple recesses 61 d to be disposedtwo-dimensionally in a plane perpendicular to the Z-axis. Also, in thefoundation layer 60, in the case where multiple protrusions 61 p areprovided, it is favorable for the multiple protrusions 61 p to bedisposed two-dimensionally in a plane perpendicular to the Z-axis. Thatis, the structural bodies 61 may be disposed in a plane parallel to thefirst major surface 60 a. Thereby, the effect of suppressing thedislocations 65 occurring at the recess 61 d increases; the proportionof the dislocations of the first semiconductor layer 10 that areannihilated by colliding with the substrate side portion 51 s due to theextension directions of the dislocations changing to horizontaldirections (directions intersecting the Z-axis) increases; and thereduction effect of the dislocation density increases. Further, thelight extraction efficiency can be greatly increased; and the luminousefficiency increases.

In other words, in the foundation layer 60, it is favorable for at leastone selected from the protrusion 61 p and the recess 61 d to be multiplyprovided and disposed two-dimensionally in a plane perpendicular to theZ-axis direction.

FIG. 14A to FIG. 14H and FIG. 15A to FIG. 15H are schematic plan viewsillustrating configurations of semiconductor light emitting devicesaccording to the first embodiment.

Namely, these drawings illustrate planar configurations and planardispositions (configurations and dispositions when viewed along theZ-axis) of the unevenness 61 (the recess 61 d and the protrusion 61 p)and the substrate unevenness 51 (the substrate protrusion 51 p and thesubstrate recess 51 d) of the first semiconductor layer 10 (e.g., thefoundation layer 60).

As illustrated in FIG. 14A to FIG. 14H and FIG. 15A to FIG. 15H, thesubstrate protrusion 51 p and the substrate recess 51 d may have variousconfigurations such as triangles, quadrilaterals (including diamonds andparallelograms), hexagons, band configurations, and the like. Themultiply-provided substrate protrusions 51 p and the multiply-providedsubstrate recesses 51 d may be disposed at the vertexes of thetriangles, the centers and the vertexes of the hexagons, and the like.Similarly, the recess 61 d and the protrusion 61 p of the firstsemiconductor layer 10 may have various configurations such astriangles, quadrilaterals (including diamonds and parallelograms),hexagons, band configurations, and the like. The multiply-providedrecesses 61 d and the multiply-provided protrusions 61 p may be disposedat the vertexes of the triangles, the centers and the vertexes of thehexagons, and the like. In addition to those recited above, variousmodifications of the planar configurations and the planar dispositionsof the unevenness 61 and the substrate unevenness 51 are possible in theembodiment.

In the substrate 50, it is favorable for at least one selected from themultiple substrate protrusions 51 p and the multiple substrate recesses51 d to be provided. Thereby, the dislocations of the firstsemiconductor layer 10 are annihilated by colliding with the substrateside portion 51 s by the extension directions of the dislocationschanging to horizontal directions (directions intersecting the Z-axis);and the dislocation density can be effectively reduced.

In the embodiment, the growth from the protrusion is suppressed whenforming the nitride semiconductor layer on the substrate having anunevenness pattern; and the crystal grown from the recess combines withitself. Thereby, a nitride semiconductor layer having excellent flatnesscan be obtained. As a result, a semiconductor light emitting devicehaving high reliability and light extraction efficiency can be realized.

The semiconductor light emitting device according to the embodiment canbe applied to, for example, bluish green, green, and red laser diodes(LDs) as well as bluish green, green, or red LEDs.

Second Embodiment

The embodiment relates to a nitride semiconductor layer growth substratefor growing a nitride semiconductor layer. The nitride semiconductorlayer growth substrate includes the substrate 50 described in the firstembodiment. In other words, the nitride semiconductor layer growthsubstrate (the substrate 50) has the substrate major surface 50 a usedto grow a nitride semiconductor layer (e.g., the semiconductorstructural body 10 s). The nitride semiconductor layer growth substratehas the multiple substrate structural bodies Sa provided in thesubstrate major surface 50 a.

Each of the multiple substrate structural bodies Sa is the substrateprotrusion 51 p provided on the substrate major surface 50 a; and thesubstrate recess 51 d is provided between the multiple substratestructural bodies Sa. Or, each of the multiple substrate structuralbodies Sa is the substrate recess 51 d provided on the substrate majorsurface 50 a; and the substrate protrusion 51 p is provided between themultiple substrate structural bodies Sa.

In this case as well, the substrate protrusion height ha, the substrateprotrusion width ra, and the substrate recess width Ra are set tosatisfy the first formula and the second formula recited above. Thereby,the occurrence of the pits Pp can be suppressed; and a semiconductorlight emitting device having a high efficiency can be constructed.

It is favorable for the ratio of the total surface area of the substrateapical portion 51 t per unit surface area of the substrate major surface50 a to the total surface area of the substrate recess 51 d the per unitsurface area to be less than 0.17. Thereby, the occurrence of the pitsPp is effectively suppressed.

It is favorable for ha/(Ta−Ra−ra) to be not more than 0.6. Also,ha/(Ta−Ra−ra) is greater than 0. Thereby, for example, the occurrence ofthe oblique surface irregular growth layer Sg can be suppressed; and thedislocation density can be effectively reduced.

The nitride semiconductor layer growth substrate includes at least oneselected from sapphire, silicon carbide (SiC), a silicon (Si) substrate,and gallium arsenide (GaAs).

Third Embodiment

The embodiment relates to a nitride semiconductor wafer.

FIG. 16A and FIG. 16B are schematic cross-sectional views illustratingthe configuration of nitride semiconductor wafers according to the thirdembodiment.

As illustrated in FIG. 16A and FIG. 16B, the nitride semiconductorwafers 210 and 211 according to the embodiment include the substrate 50and a nitride semiconductor layer (e.g., a layer including thefoundation layer 60) provided on the substrate 50.

In the nitride semiconductor wafer 210, the nitride semiconductor layerprovided on the substrate 50 includes the foundation layer 60. Thenitride semiconductor wafer 210 may be used as, for example, thefoundation portion of the functioning unit of the semiconductor lightemitting device. In other words, the nitride semiconductor wafer 210 maybe used as at least a portion of the semiconductor light emitting device110 or 120 described in the first embodiment. The nitride semiconductorwafer 210 may be used as, for example, at least a portion of asemiconductor layer included in the semiconductor light emitting device.Or, the nitride semiconductor wafer 210 may be applied to asemiconductor device that uses a nitride semiconductor layer such as atransistor (e.g., a HEMT) and the like.

In the nitride semiconductor wafer 211, the first semiconductor layer 10(including the foundation layer 60), the multilayered film body 40, thelight emitting layer 30, and the second semiconductor layer 20 areprovided on the substrate 50. In other words, the nitride semiconductorwafer 211 may be used as at least a portion of the semiconductor layerincluded in the semiconductor light emitting device.

In the nitride semiconductor wafers 210 and 211, the substrate 50 hasthe substrate structural body Sa provided in the substrate major surface50 a on the nitride semiconductor layer side. The substrate structuralbody Sa contacts the nitride semiconductor layer.

Each of the multiple substrate structural bodies Sa is the substrateprotrusion 51 p provided on the substrate major surface 50 a; and thesubstrate recess 51 d is provided between the multiple substratestructural bodies Sa. Or, each of the multiple substrate structuralbodies Sa is the substrate recess 51 d provided on the substrate majorsurface 50 a; and the substrate protrusion 51 p is provided between themultiple substrate structural bodies Sa.

In the substrate 50, the first formula and the second formula recitedabove are satisfied. In the nitride semiconductor layer, the thirdformula and the fourth formula recited above are satisfied. Thereby, theoccurrence of the pits Pp can be suppressed. Thereby, for example, anitride semiconductor wafer can be provided to construct a semiconductorlight emitting device having a high efficiency.

In the nitride semiconductor wafers 210 and 211 as well, it is favorablefor the ratio of the total surface area of the substrate apical portion51 t per unit surface area of the substrate major surface 50 a to thetotal surface area of the substrate recess 51 d per the unit surfacearea to be less than 0.17. Thereby, the occurrence of the pits Pp iseffectively suppressed.

It is favorable for ha/(Ta−Ra−ra) to be not more than 0.6. Also,ha/(Ta−Ra−ra) is greater than 0. Thereby, for example, the occurrence ofthe oblique surface irregular growth layer Sg is suppressed; and thedislocation density can be effectively reduced.

The substrate 50 includes at least one selected from sapphire, siliconcarbide (SiC), silicon (Si) substrate, and gallium arsenide (GaAs).

A nitride semiconductor layer (e.g., the semiconductor structural body10 s) is provided on the substrate 50 and includes the firstsemiconductor layer 10 that includes a layer of the first conductivitytype, the light emitting layer 30 provided on the first semiconductorlayer 10, and the second semiconductor layer 20 provided on the lightemitting layer 30, where the second semiconductor layer 20 includes alayer of the second conductivity type that is different from the firstconductivity type. The first semiconductor layer 10 is made of a nitridesemiconductor.

According to the embodiment, a semiconductor light emitting devicehaving a high efficiency, a nitride semiconductor layer growthsubstrate, and a nitride semiconductor wafer can be provided.

In the specification, “nitride semiconductor” includes all compositionsof semiconductors of the chemical formula B_(x)In_(y)Al_(z)Ga_(1-x-y-z)N(0≦x≦1, 0≦y≦1, 0≦z≦1, and x+y+z≦1) for which the compositionalproportions x, y, and z are changed within the ranges respectively.“Nitride semiconductor” further includes group V elements other than N(nitrogen) in the chemical formula recited above, various elements addedto control various properties such as the conductivity type and thelike, and various elements included unintentionally.

In the specification of the application, “perpendicular” and “parallel”refer to not only strictly perpendicular and strictly parallel but alsoinclude, for example, the fluctuation due to manufacturing processes,etc. It is sufficient to be substantially perpendicular andsubstantially parallel.

Hereinabove, exemplary embodiments of the invention are described withreference to specific examples. However, the invention is not limited tothese specific examples. For example, one skilled in the art maysimilarly practice the invention by appropriately selecting specificconfigurations of components included in semiconductor light emittingdevices or nitride semiconductor wafers such as substrates, bufferlayers, foundation layers, semiconductor layers, light emitting layers,electrodes, and the like from known art; and such practice is includedin the scope of the invention to the extent that similar effects areobtained.

Further, any two or more components of the specific examples may becombined within the extent of technical feasibility and are included inthe scope of the invention to the extent that the purport of theinvention is included.

Moreover, all semiconductor light emitting devices, nitridesemiconductor layer growth substrates, and nitride semiconductor waferspracticable by an appropriate design modification by one skilled in theart based on the semiconductor light emitting devices, the nitridesemiconductor layer growth substrates, and the nitride semiconductorwafers described above as embodiments of the invention also are withinthe scope of the invention to the extent that the spirit of theinvention is included.

Various other variations and modifications can be conceived by thoseskilled in the art within the spirit of the invention, and it isunderstood that such variations and modifications are also encompassedwithin the scope of the invention.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the invention.

1. (canceled) 2: A substrate, the substrate having a substrate surface,the substrate surface including a plurality of protrusions, theprotrusions including a first apical face and a second apical facenearest to the first apical face, the first apical face having a firstcentroid, the second apical face having a second centroid, the firstcentroid aligning with the second centroid along a second axis; and haand ra satisfyingra/(2·ha)<0.7, where ha is a height of the protrusion, and ra is a widthof the first apical face along the second axis. 3: The substrateaccording to claim 2, wherein a ratio of a total surface area of apicalfaces of the protrusions per unit surface area of the substrate surfaceto a total surface area of a bottom face of the substrate surface perthe unit surface area of the substrate surface is less than 0.17. 4: Thesubstrate according to claim 2, wherein ha/(Ta−Ra−ra) is not more than0.6, where Ta is a distance between the first centroid and the secondcentroid along the second axis and Ra is a width of the bottom facealong the second axis. 5: The substrate according to claim 2, whereinthe substrate includes at least one of sapphire, silicon carbide (SiC),silicon (Si), and gallium arsenide (GaAs). 6: The substrate according toclaim 2, wherein Ra is a width of the bottom face along the second axis,the ha is 0.5 micrometers or more and 3 micrometers or less, the ra is0.5 micrometers or more and 4 micrometers or less, and the Ra is 0.5micrometers or more and 4 micrometers or less. 7: The substrateaccording to claim 2, wherein the ra/Ra is not more than 0.6, and whereRa is a width of the bottom face along the second axis. 8: The substrateaccording to claim 7, wherein the ra/Ra is not less than 0.25. 9: Thesubstrate according to claim 3, the ratio of the total surface area ofthe apical faces per the unit surface area of the substrate surface tothe total surface area of the bottom face per the unit surface area ofthe substrate surface is not more than 0.11. 10: The substrate accordingto claim 7, wherein ha/(Ta−Ra−ra) is not more than 0.6, where Ta is adistance between the first centroid and the second centroid along thesecond axis. 11: The substrate according to claim 4, wherein theha/(Ta−Ra−ra) is not more than 0.59. 12: The substrate according toclaim 10, wherein the ha/(Ta−Ra−ra) is not more than 0.59. 13: Thesubstrate according to claim 4, wherein the ha/(Ta−Ra−ra) is not morethan 0.5. 14: The substrate according to claim 10, wherein theha/(Ta−Ra−ra) is not more than 0.5. 15: The substrate according to claim2, wherein each of the first apical face and the second apical face ishexagonal. 16: The substrate device according to claim 15, wherein aside of the first apical face is parallel to a side of the second apicalface. 17: The substrate according to claim 2, wherein each of the firstapical face and the second apical face is regular hexagonal. 18: Thesubstrate according to claim 2, wherein each of the first apical faceand the second apical face is triangular. 19: The substrate according toclaim 18, wherein a side of the first apical face is parallel to a sideof the second apical face. 20: The substrate according to claim 2,wherein each of the first apical face and the second apical face isregular triangular. 21: The substrate according to claim 2, wherein eachof the first apical face and the second apical face is triangular, and aside of the first apical face located on an extension of a side of thesecond apical face. 22: The substrate according to claim 21, whereineach of the first apical face and the second apical face is rightregular triangular.